`include "defines.v"

module if_reg(
    
    input                     clk,
    input                     rst,
    input                     if_stall_i,

    input  wire [`RAM_BUS]    if_pc_i,
    input  wire [31 : 0]      if_inst_i,
    input  wire               if_reg_valid_i,

    output reg  [`RAM_BUS]    if_pc_o,
    output reg  [31 : 0]      if_inst_o,
    output reg                if_reg_valid_o

);

    always@(posedge clk)begin
        if(rst == `RST )begin
            if_pc_o <= 0;
            if_inst_o <= 0;
            if_reg_valid_o <= 0;
        end
        else if(if_stall_i)begin
            if_pc_o <= if_pc_o;
            if_inst_o <= if_inst_o; 
            if_reg_valid_o <= if_reg_valid_o;
        end
        else begin
            if_pc_o <= if_pc_i;
            if_inst_o <= if_inst_i;
            if_reg_valid_o <= if_reg_valid_i; 
        end
    end




endmodule